For the first time, we demonstrate the hybrid integration of dual distributed feedback (DFB) quantum cascade lasers (QCLs) on a silicon photonics platform using an innovative 3D self-aligned flip-chip assembly process. The QCL waveguide geometry was predesigned with alignment fiducials, enabling a sub-micron accuracy during assembly. Laser oscillation was observed at the designed wavelength of 7.2 μm, with a threshold current of 170 mA at room temperature under pulsed mode operation. The optical output power after an on-chip beam combiner reached sub-milliwatt levels under stable continuous wave operation at 15 °C. The specific packaging design miniaturized the entire light source by a factor of 100 compared with traditional free-space dual lasers module. Divergence values of 2.88 mrad along the horizontal axis and 1.84 mrad along the vertical axis were measured after packaging. Promisingly, adhering to i-line lithography and reducing the reliance on high-end flip-chip tools significantly lowers the cost per chip. This approach opens new avenues for QCL integration on silicon photonic chips, with significant implications for portable mid-infrared spectroscopy devices.
Keywords:
silicon photonics; flip-chip integration; quantum cascade laser; mid-infrared spectroscopy
Mid-infrared spectroscopy is a highly discriminatory technique used for chemical analysis of gases, liquids and solids. In particular, the spectral region (1350–1410 cm−1) covers the fundamental vibrational transitions of CH3, the basis for analysis of aliphatic hydrocarbons groups [1]. Spectroscopic techniques allow non-destructive and label-free quantitation of a wide variety of samples [2], for instance, oil-in-water, which is crucial for industrial waste evaluation, environment protection and drinking water analysis. Quantum Cascade Lasers (QCLs) are ideal light sources due to their flexible energy bandgap engineering allowing one to design and make lasers with almost any specific emission spectrum in the MIR region from 4 μm to >10 μm, as well as in the THz region [3]. Conventionally, absorption spectroscopy can employ two collimated QCLs as one for measuring traces of analyte while the other for simultaneous background reference, and combines them with free-space beam combiner. However, this free-space routing leads to a bulky setup which is prone to mechanical disturbances and requires expensive optical and opto-mechanical components. The integration of QCLs on photonic integrated circuits (PIC) tends to be an appealing solution, allowing for robustness as there are no moving parts, as well as a reduced fingerprint of the device, and the potential of low-cost production.
Silicon photonics (SiPh) has evolved at a rapid rate by leveraging the extremely mature silicon manufacturing ecosystem as a result of decades of CMOS development [4]. A diverse portfolio of photonic sensors can potentially be integrated on a single silicon chip. In recent years, there has been a growing number of demonstrations of integrated long-wavelength silicon devices, including lasers [5,6], resonators [7,8], modulators [9,10], couplers [11], and multiplexers [12]. Among these components, optical amplifiers have proven to be the most challenging due to their distinct material system and optical interface to passive circuits. Monolithic integration tends to be an ultimate approach where a few demonstrators appeared [13,14,15,16]. However, specific process developments are always required, such as either regrowth or ion implantation. According to the SiPh roadmap of 2024 [17], both heterogeneous and monolithic integration are still at a lower technology readiness level (TRL). By contrast, hybrid integration is appealing as a rapid solution due to its mature technology developed in the near-infrared range [18,19,20]. With regard to the integration of power-hungry QCLs, which requires high thermal conductivity between lasers and silicon substrate, solder-based flip-chip bonding has intrinsic higher thermal conductivity than adhesive bonding which is commonly used in the other approaches.
Germanium (Ge) has low losses in the 2–14 μm wavelength range [21,22,23], which together with its compatibility with standard CMOS processes, makes it the platform of choice for the implementation of mid-infrared PICs. For example, a functional passive circuit sensor over the 6.5–7.5 μm range has been demonstrated based on Ge-on-Si waveguides from our group [24]. As we are now placing efforts on the integration of QCLs on this platform, we reported our first QCL integration results during the IEEE SiPh conference 2023 [25]. Although the initial laser could work only under pulsed operation, it was still very promising by showing the proof-of-concept of 3D self-alignment assembly.
In this paper, we elaborate more details on the design, fabrication, assembly, characterization and package of integrated beam combined QCL lasers. The opto-mechanical interface between the Ge-on-Si chip and the InP-based DFB QCL was carefully co-designed to maximize the coupling efficiency between the QCL’s and Ge’s waveguides. Figure 1 shows the 3D self-alignment approach implemented in this paper. The in-plane alignment can be realized by coarse aligning with the lithography markers and vertical alignment can be ensured by mechanical stopper, similarly to Ref. [26]. The bonding was followed by a reflow process to melt the solder which provides capillary force for 3D self-alignment. The optimized solder printing process leads to continuous wave (CW) operational lasing with sub-milliwatt output power. Furthermore, we packaged the beam combined chip in a high heat load (HHL) package that included a thermoelectrical cooler (TEC) and a collimating lens. Both optical power and beam quality were characterized after packaging, resulting in the successful miniaturization of the entire light source module.
Figure 1. Schematic representation of the 3D self-alignment flip-chip assembly.
To achieve optimal coupling efficiency, the optical mode overlap between the QCL facet and the Ge waveguide facet was simulated by using Ansys, Inc. Lumerical FDTD, Irvine, CA, USA. A Ge thickness of 2 μm was selected to ensure consistency with our platform development [24]. Typically, a spot size converter with an inverse taper is employed to efficiently couple light from III–V to Si/Si3N4 waveguides in the telecom range. However, this approach requires waveguide features to be a few hundred nanometers in size. Since we aim to adhere to i-line contact lithography processes to significantly reduce costs, we used an adiabatic taper to expand the mode field for maximum matching with the mode in the QCL. Figure 2a presents the simulated coupling efficiency for various widths of the Ge waveguide. The highest coupling efficiency, 61.8%, was achieved using a 10 μm wide Ge taper with no gap. Notably, the coupling efficiency is relatively insensitive to the longitudinal gaps due to the long wavelength; even a 2 μm gap can still provide a reasonable coupling efficiency of 55%.
Figure 2. (a) Simulation of coupling efficiency at different Ge width and gaps, (b) Misalignment simulation, (c) Experimental measurement result of 1 × 2 MMI combiner/splitter, insertion shows the simulated top-view optical profile at 7.2 μm wavelength.
Figure 2b illustrates the impact of misalignment in both the in-plane (Y) and vertical (Z) directions. There is an inherent trade-off between achieving higher coupling efficiency and ensuring larger alignment tolerance. While a 10 μm width for the Ge waveguide offers the highest coupling efficiency, a 15 μm width provides improved tolerance to misalignment. Therefore, we incorporated both in the experimental assembly. Along the vertical direction, those pedestals sticking out of Si cavity will physically support the QCL. The pillars on the Si PIC were designed to accommodate the geometry of the QCL, with dimensions slightly smaller by ±15 μm laterally and ±20 μm along the cavity to account for uncertainties in QCL cleaving. Due to the high aspect ratio of the laser (several millimeters in length and hundreds of microns in width), significant rotational misalignment is not anticipated.
Single TM mode waveguide with a width of 3.6 μm was employed to direct light to a precisely designed on-chip beam combiner/splitter. A multimode interference (MMI) coupler was selected for the target wavelength of 7.2 μm, owing to its inherent advantage of broad bandwidth. The optimized interference region is 20 μm wide and 110 μm long. As depicted in Figure 2c, the power splitting ratio varies by less than 10% over the wavelength range from 6.6 μm to 7.6 μm. This stability is highly advantageous for dual-comb spectroscopy, wherein two QCL comb lasers with slightly different repetition rates must be combined and directed to a photodetector [27]. A bend radius of 300 μm was implemented throughout the entire circuit, resulting in negligible bending loss.
The fabrication process flow for Ge-on-Si PIC followed by flip-chip integration of the DFB QCLs is presented schematically in Figure 3. At first, 2 μm thick Ge layer was epitaxially grown on a 8-inch Si wafer. On top of the Ge layer, high-resolution positive tone MIR701 photoresist was spin-coated and patterned to form waveguide structures using a standard i-line lithography process (Figure 3a). Owing to prior optimizations, MIR701 allowed a minimum feature size of 800 nm with the most smooth sidewall by reflowing it at 110 °C for 1 min before development. The patterned MIR701 was used as a soft mask to etch Ge layer and fabricate Ge waveguides on silicon using reactive ion etching (RIE) with a mixture of CF4, SF6 and H2 (Figure 3b). Afterwards, the remaining resist mask was stripped by rinsing in acetone, IPA and DI water followed by oxygen plasma. The next step was to fabricate the recess and Si pedestals in the Si wafer where the QCLs would be resting to achieve vertical alignment of the QCL’s active region with the Ge waveguide. The Si pedestal and recess design was first patterned in thick AZ10XT photoresist (Figure 3c) which acted as masking layer for deep Si RIE step. However, to achieve an uniform coupling facet in Ge-on-Si PIC, AZ10XT was designed in such a way that an additional RIE step was required to remove Ge on top of the Si pedestals and simultaneously define the coupling facet as well, as shown in Figure 3d. Finally, deep RIE was used to define 20 ± 1 μm deep recess in Si wafer (Figure 3e).
Figure 3. Process flow for self-assembling QCL on Ge-on-Si PIC.
Subsequently, a 40 nm thick AlOx layer was deposited using electron beam evaporation to act as an etching stopper due to its high etch selectivity, followed by an anti-reflection (AR) Si3N4 layer deposition using a conformal PECVD deposition technique (Figure 3f). This was followed by sputter deposition of a TiW adhesion layer (25 nm) and a 350 nm thick Al seed layer which were patterned using standard lithography and wet etching techniques (Figure 3g). Here, H3PO4/HNO3/HAc was used to remove the Al layer, followed by H2O2 to remove the TiW layer, ensuring that only the conductive pattern remains for the next step. Then, a standard Electroless Nickel Immersion Gold (ENIG) plating was conducted to achieve 3 ± 1 μm thick ENIG pads (Figure 3h) inside the Si recess as well as on the Si surface for wire bonding and further characterizations. The top layers of Si3N4 and AlOx were then removed, resulting into the presence of these materials only on the facets (Figure 3i,j). A combination of RIE dry and BOE wet etching was utilized to ensure a smooth waveguide surface. A 990 nm thick TiO2 layer was deposited by electron beam evaporation directionally on the output facet to maximize the optical transmission (Figure 3k). After completing these steps, the chip was diced into separate dies ready for assembly. Finally, the 3D self-alignment flip-chip integration was performed (Figure 3l) which will be discussed in the subsequent section.
The fabricated Ge-on-Si PIC was inspected in a scanning electron microscope (SEM) to characterize the waveguide and coupling facet quality. SEM micrograph presented in Figure 4a shows the low sidewall roughness achieved using i-line contact lithography. Despite this, a propagation loss of approximately 7.5 dB/cm was measured for the wavelength of 7.2 μm, implying that a significant portion of the loss originates from the interface between Si and Ge. IMEC Leuven, Belgium has developed a new technology named Ge-on-Nothing for solar cells application, which shows promise for use here as well, effectively avoiding the interfacial defects [28]. Vertical etching of the cavity, as illustrated in Figure 4b, is essential to avoid a positive angle, which would hinder the QCL from moving forward to the Ge facet. Since an uncoated Ge surface reflects 36% of light in the mid-infrared wavelength range, an effective anti-reflection (AR) coating is crucial to reduce reflections. From Figure 4c, a uniform Si3N4 deposition can be seen in a conformal manner, ensuring thorough coverage of the facet. The optimal thickness for minimal reflection at the target wavelength was determined through both FDTD simulation and experimentation, with 1.117 μm of Si3N4reducing reflection down to 1.2% at the target wavelength.
Figure 4. SEM images of (a) single mode Ge waveguide, (b) vertical 20 μm deep etched Si recess, (c) Si3N4AR coating on coupling facet.
The optical image of the fabricated Ge-on-Si PIC is shown in Figure 5a. The PIC was designed to have versatile geometry which could accommodate QCLs having different lengths (i.e., 1.5 mm, 2.25 mm, and 3.0 mm), corresponding to three large rectangular QCL building blocks intentionally designed to prevent solder pile-up at the rear of the QCL during assembly. Additionally, the ENIG metal layer inside the cavity was specifically designed with a forward offset of 20 μm with respect to the pillars, providing a capillary pulling force during the solder reflow step for the self-alignment of QCL with the Ge facet along the longitudinal direction. The symmetric shape across the x-axis ensures that the molten solder will center the QCL, minimizing lateral misalignment. Dedicated alignment markers were also incorporated in the ENIG layer to facilitate the coarse alignment during the assembly process.
Figure 5. Microscope images of Ge-on-Si PIC (a,b) and InP-based QCL (c), step height profile of Ge-on-Si PIC with ~4 μm thick ENIG layer (d) and QCL (e).
